1. Field of the Invention
The present invention relates generally to a system and method for designing integrated circuits fabricated by a semiconductor manufacturing process and, more particularly, to a system and method for designing integrated circuits to enhance manufacturability and, hence, yield of a semiconductor fabrication process used to produce the integrated circuits.
2. Description of the Prior Art
The semiconductor manufacturing industry is continually evolving semiconductor designs and fabrication processes and developing new processes to produce smaller and smaller geometries of the designs being manufactured, because smaller semiconductor devices typically consume less power, generate less heat, and operate at higher speeds than larger devices. Currently, a single integrated circuit chip may contain over one billion patterns. Consequently, integrated circuit designs and semiconductor fabrication processes are extremely complex, since hundreds of processing steps may be involved. Occurrence of a mistake or small error at any of the design or process steps may necessitate redesign or cause lower yield in the final semiconductor product, where yield may be defined as the number of functional devices produced by the process as compared to the theoretical number of devices that could be produced assuming no bad devices.
Improving time-to-market and yield is a critical problem in the semiconductor manufacturing industry and has a direct economic impact on the semiconductor industry. In particular, a reduced time-to-market and higher yield translate into earlier availability and more devices that may be sold by the manufacturer.
Semiconductor integrated circuit (IC) design and manufacturing processes have become increasingly challenging with each new technology node. Classically, the communication of IC requirements between design and manufacturing has been enabled through a set of global and comprehensive design rules. However, with the emergence of sub-wavelength photolithography, the nonlinearity of the pattern transfer process onto semiconductor material such as silicon has increased dramatically. Due to this phenomenon, the effectiveness of the conventional IC design methodology has been significantly decreasing.
The traditional global design rule approach suffers from the following paradox between IC layout density and manufacturability. To achieve tighter designs, the design rules need to be as aggressive as possible, while wafer manufacturing is enabled using complicated sub-wavelength technology. This creates more and more manufacturability problems. For example, 65 nm design rules call for a much smaller feature size and pattern pitch than 90 nm design rules, whereas the pattern resolution improvement from manufacturing equipment expected for 65 nm technology is somewhat limited. To alleviate printability problems of some “difficult” layout patterns, it is sometimes necessary to relax design dimensions, which translates into more relaxed global design rules for physical layout synthesis. Subsequently, this results in loss of density.
Considered in more detail, FIG. 1 illustrates typical design and manufacturability trade-offs. In FIG. 1(a), the horizontal axis 101 is the density/manufacturability axis, in which moving to the left means lower pattern density but better manufacturability, and moving to the right means higher pattern density but poorer manufacturability. The vertical axis 102 is the distribution of patterns for a design. The threshold 103 marks the boundary for manufacturability problems, and 104 marks the boundary for potential density improvements. The area between the two thresholds 103 and 104 is where acceptable compromises between design and manufacturing are achieved.
As shown in FIG. 1(a), the distribution curve 105 represents a typical design associated with an aggressive design rule, where although most of the design patterns 106 fall into good compromise areas, a significant portion of the design will potentially have manufacturability problems, as indicated by the shaded area 107. Conversely, the area 108, that allows design improvements, is minimal, because the design rules used are already aggressive.
On the other hand, the distribution 109 shows a typical design with relaxed design rules. As can be seen, the manufacturability problems are minimized, but the design is not optimized in terms of density, and there is opportunity for design improvement. As an outcome, such a design may not meet the targeted chip size.
However, well-balanced design rules would result in a well-centered curve, as shown in FIG. 1(b), in which the distribution is more even between good manufacturability and design density. In this case, the quality threshold is determined based on a distribution where the total area of the design that has potential manufacturability problems is smaller than a certain predetermined value (e.g., 0, which means no manufacturability problem is allowed). The distance between the quality threshold and the manufacturability threshold is referred to as “process margin.”
One approach that the semiconductor industry is pursuing is to incorporate manufacturability check or verification, primarily photolithography related, into the front-end design. Manufacturability is verified during physical layout creation, which attempts to eliminate potential manufacturing difficulty in the final design tape-out.
While potentially preventing the problem at the back-end, this front-end design approach has many drawbacks. These drawbacks include the following:
1. A front-end oriented technique essentially interrupts the current front-end design flow, which is well-established for many IC designers. The disturbance to the existing flow is even more severe when encountering a tightly integrated logic/high level synthesis, physical design, and timing verification flow. In addition, the front-end design flow is already complex enough due to the difficulty in getting timing closure. The introduction of additional constraints (i.e., manufacturability) can potentially introduce even more complex flows and more design iterations.
2. It requires extensive tool support and integration from the currently well-established and mature design tools.
3. It requires knowledge and expertise in manufacturing processes, which the front-end designers typically lack.
4. Most of all, the front-end oriented approach requires a paradigm shift from the traditional “throw-over-the-wall” approach and requires a much more extensive and frequent feedback from manufacturing to the design side. This may potentially increase product time-to-market.
Thus, it would be desirable to provide an IC design system and method which overcome the above limitations and disadvantages of conventional systems and techniques and facilitate IC designs having improved manufacturability. It is to this end that the present invention is directed. The various embodiments of the present invention provide many advantages over conventional IC design methods and systems.